Increased speed of operation has been a constant design goal in the development of digital computer systems, and efforts toward this goal have proceeded on all levels including improvements in central processor architecture, in input/output systems, and in the electronic logic circuits used. At the electronic logic circuit level, improvements over the years in integrated circuits have produced generations of logic circuits having shorter switching times, pemitting higher clock speed operation in computers. However, as clock speed and computer system complexity increased, other problems were encountered which tended to limit the maximum speed of operation of computers. The problems of ground or power supply noise and the need for greater density to bring circuits physically closer have limited progress in inceasing the speed and size of computers.
The problem of ground noise is very serious, particularly for single ended logic gates which use a single conductor connecting the output of one gate to the input of another gate with the common system signal ground as the return path. In high speed operation, the ground at the circuit module level in the immediate vicinity of the integrated circuits may contain a significant amount of noise induced by the switching on and off of numerous nearby logic gates. This ground noise can cause unintended triggering of other gates, which of course cannot be tolerated and which effectively serves to limit the speed of such systems. It is difficult or impossible to filter out the types of ground noise and power supply noise encountered, since some of it is due to groups of circuits which may switch rather infrequently, i.e. only after a large number of clock pulses, which introduces a low frequency component to the noise which is very difficult to filter out, especially at the chip or module level. A related problem with prior art systems is difficulty in power supply regulation due to surges in demands as groups of devices switch.
Ground return noise can be alleviated by using logic circuits which provide an output and its complement, requiring a pair of conductors to run from each gate to the input or inputs of a succeeding gate or gates. This greatly allevaites the ground return noise problem, although noise introduced through power supplies due to the low frequency component referred to above are still encountered. But the use of logic having a signal and complement creates a density problem, in terms of the number of pins available at the chip or module level, and the circuit board space required for all the conductors. This in turn leads to a physically larger computer with longer than desired path lengths between logic circuits.
A related density problem with present-day designs is the relatively inefficient use of chip and circuit board space because of the need for a great number of latches. Present-day systems, which might be termed loosely synchronous, provide a number of levels of logic between successive latches. Typically eight levels of static logic gates may be interposed between successive clocked latches, although a greater or lesser number may be used. In such systems the clock period must be slow enough to ensure that the logic signals will propagate through the intervening levels of static gates to the next latch in time for the next clock pulse. It would therefore be desirable in terms of shortening the clock period to have more latches with fewer levels of static logic gates between them. However, each latch circuit typically will take up as much space as four or more static logic gates, and their financial cost is also proportionately higher. Therefore a compromise must be made as to numbers of latches and numbers of levels of static logic between them, and the clock period then must be made slow enough to allow for the required settling and propagation time between latches.